In high speed multiboard computing systems it is advantageous to minimize the number of signals that must be transmitted from circuit board to circuit board. As an initial matter, by minimizing the number of signals being transferred, the number of required connector pins can physically be minimized. Notwithstanding, even if sufficient connector pins are available, it is still undesirable to use all of the available connector pins for carrying switching signals. Rather, it good design practice to space apart the high speed switching signals across the connector such that crosstalk and noise can be controlled. Further, those pins which are not being used for switching signals can instead be used, such as in the case of motherboard to daughter board connections, as ground pins. By spacing apart the connector pins and using the remaining pins to couple the ground planes in circuit board to circuit board connections, problems with drift in the ground planes towards the power supply can be controlled.
One particular instance when minimization of the signals passing through a connector is highly advantageous is when data is being sent from a motherboard to one or more memory boards employing dynamic random access memories (DRAMs). In this case, the goal is not only to minimize the signals flowing through the connectors but also to support a standard hardware design which will allow for the use of different types of DRAMs having differing operating parameters. For example, one of the major problems in controlling DRAM memory systems is adjusting for differences in device signal to signal timing in order to maximize performance. In the past, system timing was typically varied using signals provided by a control signal generator and discrete gates and delay lines. This method had substantial disadvantages. With each DRAM of differing performance parameters, a new hardware design was required. Further, if the memory devices and the associated control circuitry were on different circuit boards, the number of control signals passing through the connectors became excessive leading to electrical noise problems. Finally, the additional hardware required simply added complexity and cost to the design and took up valuable board space.
Thus, a need has arisen for apparatus, systems and methods for minimizing the number of signals being passed through a connector. Further, a need has arisen for apparatus, systems, and methods providing flexible memory control. Such apparatus, systems and methods would allow for the use of memory devices of varying performance parameters in a single design while minimizing the amount of control hardware required.